SH7763 Datasheet, PDF (1372/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.9 Command Timeout Control Register (CTOCR)
CTOCR specifies the period for generating a timeout for the command response.
When the command response is received, CTOCR continues counting the transfer clock and enters
the command timeout error state when the number of transfer clock cycles reaches the number
specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is
set. To perform command timeout error handling, the command sequence should be aborted by
setting the CMDOFF bit to 1 and then clearing the CTERI flag.
Bit: 7
6
5
4
3
2
1
0
— — — — — — — CTSEL0
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name Value R/W Description
7 to 1 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
CTSEL0 1
R/W 0: 128 transfer clock cycles from command
transmission completion to response reception
completion
1: 256 transfer clock cycles from command
transmission completion to response reception
completion
Note: If an R2 response (17-byte command response) in MMC mode is requested and CTSEL0 is
cleared to 0, a timeout is generated during response reception. Therefore, set CTSEL0 to 1.
Rev. 1.00 Oct. 01, 2007 Page 1306 of 1956
REJ09B0256-0100