SH7763 Datasheet, PDF (591/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(27) PCI Cache Snoop Address Register 1 (PCICSAR1)
PCICSAR1 specifies the address to be compared with the PCI address requested by an external
device.
Refer to section 13.4.4 (7), Cache Coherency.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CADR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CADR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: — — — — — — — — — — — — — — — —
Bit
31 to 0
Bit Name
CADR
Initial
Value
All 0
R/W
SH: R/W
PCI: —
Description
Address to be compared
Specify address to be compared with the PCI address
requested by external PCI devices
Rev. 1.00 Oct. 01, 2007 Page 525 of 1956
REJ09B0256-0100