SH7763 Datasheet, PDF (881/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W Description
3
PHYI
0
R
ET_PHY-INT Interrupt
Indicates the state of the ET_PHY-INT pin input from
the PHY-LSI.
0: ET_PHY-INT pin is not asserted
1: ET_PHY-INT pin is asserted
The signal polarity of the ET_PHY-INT pin can be set
by PIPR.
2
LCHNG 0
R/W Link Signal Change
Indicates that the ET_LNKSTA signal input from the
PHY-LSI has changed from high to low or low to high.
However, signal changes may be detected at the timing
at which the ET_LNKSTA function was selected using
PACR of the GPIO.
To check the current Link state, refer to the LMON bit in
the PHY status register (PSR).
0: Change in the ET_LNKSTA signal has not been
detected
1: Change in the ET_LNKSTA signal has been
detected (high to low or low to high)
1
MPD
0
R/W Magic Packet Detection
Indicates that a Magic Packet has been detected on the
line.
0: Magic Packet has not been detected
1: Magic Packet has been detected
0
ICD
0
R/W Illegal Carrier Detection
Indicates that the PHY-LSI has detected an illegal
carrier on the line. If a change in the signal input from
the PHY-LSI occurs in a period shorter than the
software recognition period, the correct information may
not be obtained. Refer to the timing specification for the
PHY-LSI used.
0: PHY-LSI has not detected an illegal carrier on the
line
1: PHY-LSI has detected an illegal carrier on the line
Rev. 1.00 Oct. 01, 2007 Page 815 of 1956
REJ09B0256-0100