SH7763 Datasheet, PDF (437/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
(3) Read-Strobe Negate Timing
When the SRAM interface is used, the negation timing of the strobe signal during a read operation
can be specified through the RDH bit in CSnWCR.
Rev. 1.00 Oct. 01, 2007 Page 371 of 1956
REJ09B0256-0100