SH7763 Datasheet, PDF (1575/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.3 Interrupt Flag Register 2 (IFR2)
IFR2 is an interrupt flag register for SURSS, SURSF, CFDN, SOF SETC, and SETI. When each
flag is set to 1 and an interrupt is enabled in the corresponding bit of IER2, an interrupt request
(USBFI0 or USBFI1) specified by the corresponding bit in ISR2 is issued to INTC.
Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear
bits, access the register so that 0 should be written only to the bits for the interrupt sources to be
cleared and that 1 should be written to the other bits. Do not use a bit field declaration of the C
language to clear bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R
RR
R
RR
R
RR
R
RR
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — SURSS SURSF CFDN SOF SETC SETI
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value
31 to 8 
Undefined
7, 6 
All 0
5
SURSS 0
R/W Description
R Reserved
These bits are always read as undefined value. Write
value should always be 0.
R Reserved
These bits are always read as 0. The write value
should always be 0.
R Suspend/Resume Status
Status bit indicating the state of the bus
0: Normal state
1: Suspend state
Rev. 1.00 Oct. 01, 2007 Page 1509 of 1956
REJ09B0256-0100