SH7763 Datasheet, PDF (408/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W
23

0
R
22 to 20 IWRWS 111
R/W
19

0
R
18 to 16 IWRRD
111
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Read-Write to Same Space
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-write cycles to
the same space. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Read-Read to Different Spaces
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-read cycles to
different spaces. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 342 of 1956
REJ09B0256-0100