SH7763 Datasheet, PDF (707/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
16.4.2 PLL Control Register (PLLCR)
PLLCR is a 32-bit readable/writable register that enables or disables clock output from the
CLKOUT pin. PLLCR can be accessed only in longwords.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−−− −−−−−−−− −−−−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − − − − − − − − − − − − ^{CKOFF CKONE}
Initial value: 0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W: R R R R R R R R R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 15 —
All 0
R
Reserved
The write value should be the same as the initial
values.
14, 13 —
All 1
R
Reserved
The write value should be the same as the initial
values.
12 to 2 —
All 0
R
Reserved
The write value should be the same as the initial
values.
1
CKOFF 0
R/W CLKOUT Output Stop
0: Clock is output from the CLKOUT pin.
1: Clock is not output from the CLKOUT pin.
(The pin level is low.)
0
Note:
CKONE 1
R/W Clock Output Enable
Selects whether to output clock from the CLKOUT pin
or tie the CLKOUT pin to a low level during software
standby mode.
0: Tied to a low level
1: Clock is output
* Depends on the clock operating mode that is selected by the MD0 to MD2 pin settings.
Rev. 1.00 Oct. 01, 2007 Page 641 of 1956
REJ09B0256-0100