SH7763 Datasheet, PDF (725/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 Watchdog Timer and Reset (WDT)
17.5 Status Pin Change Timing during Reset
17.5.1 Power-On Reset by PRESET
A power-on reset is to initialize the on-chip PLL circuit when this LSI goes to the power-on reset
state by the PERSET pin low level input and then it is necessary to ensure the synchronization
settling time of the PLL circuit. Therefore, do not input high level to the PRESET pin during the
PLL synchronization settling time. The PLL synchronization settling time is the total value of the
PLL1 synchronization settling time and the PLL2 synchronization settling time.
After the PRESET pin input level is changed from low level to high level, the reset state is
continued during the reset holding time in the LSI. The reset holding time is 20 clock cycles of the
EXTAL pin input clock and thereafter equal to or more than 45 clock cycles of the peripheral
clock (Pck0).
The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that
indicates a normal operation is synchronous with the peripheral clock (Pck0) and asynchronous
with both the EXTAL pin input clock and the CLKOUT pin input clock.
(1) Turning On Power Supply
When turning on power supply, the PRESET pin input level should be low level. And the TRST
pin input level should be low level to initialize the H-UDI.
Rev. 1.00 Oct. 01, 2007 Page 659 of 1956
REJ09B0256-0100