SH7763 Datasheet, PDF (1531/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.3 HcCommandStatus Register (USBHCS)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — — — — SOC[1:0]
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — — — — — — BLF CLF HCR
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R/W R/W R/W
Bit
31 to 18
Bit Name

17, 16 SOC[1:0]
15 to 3 
2
BLF
1
CLF
Initial Value R/W
All 0
R
All 0
R
All 0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0
ScheduleOverrunCount
These bits increment every time the
SchedulingOverrun bit in HcInterruptStatus is set.
The count wraps from 11 to 00.
Reserved
These bits are always read as 0. The write value
should always be 0
BulkListFilled
When set, this bit indicates there is an active ED
on the Bulk List. The bit can be set by either
software or the Host Controller. The bit is cleared
by the Host Controller each time it begins
processing the head of the Bulk List.
ControlListFilled
When set, this bit indicates there is an active ED
on the Control List. The bit can be set by either
software or the Host Controller. The bit is cleared
by the Host Controller each time it begins
processing the head of the Control List.
Rev. 1.00 Oct. 01, 2007 Page 1465 of 1956
REJ09B0256-0100