SH7763 Datasheet, PDF (1469/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Audio Codec Interface (HAC)
33.3.7 TX Status Register (HACTSR)
HACTSR is a 32-bit read/write register that indicates the status of the HAC TX controller. Writing
0 to the bit will initialize it.
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − ^{CMD CMD PLT PRT}
AMT DMT FRQ FRQ
−−
−
−−
−−
−
−
−
Initial value:
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R R R R R R R R R R R R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−
−
−
−
−
− − PLT PRT
FUN FUN
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R/W R/W R R R R R R R R
Initial
Bit
Bit Name Value
31
CMDAMT 1
30
CMDDMT 1
29
PLTFRQ 1
28
PRTFRQ 1
27 to 10 
All 0
R/W
R/W*²
R/W*²
R/W*²
R/W*²
R
Description
Command Address Empty
0: CSAR Tx buffer contains untransmitted data.
1: CSAR Tx buffer is empty and ready to store data.*¹
Command Data Empty
0: CSDR Tx buffer contains untransmitted data.
1: CSDR Tx buffer is empty and ready to store data.*¹
PCML TX Request
0: PCML Tx buffer contains untransmitted data.
1: PCML TX buffer is empty and needs to store data. In
DMA mode, writing to HACPCML will automatically
clear this bit to 0.
PCMR TX Request
0: PCMR Tx buffer contains untransmitted data.
1: PCMR TX buffer is empty and needs to store data. In
DMA mode, writing to HACPCMR will automatically
clear this bit to 0.
Reserved
Always 0 for read and write.
Rev. 1.00 Oct. 01, 2007 Page 1403 of 1956
REJ09B0256-0100