SH7763 Datasheet, PDF (488/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Initial
Bit
Bit Name Value R/W Description
63 to 3 
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0 SMS
000
R/W SDRAM Mode Select
These bits initialize the DDR-SDRAM at a power-on or
after release of a reset. If this bit is set by software, the
following commands are issued. For details on the
initialization procedure, see section 12.5.2, DDR-
SDRAM Initialization Sequence. After the DDR-
SDRAM has been initialized, normal operation (000) is
specified.
000: Normal operation
001: The NOP command is issued (valid only when the
DCE bit in MIM is set to 1).
010: The PREALL command is issued (valid only when
the DCE bit in MIM is set to 1).
011: The M_CKE pin is enabled. At that time, the
DESELECT command is issued (valid only when
the DCE bit in MIM is set to 1).
100: The REFA (auto) refresh command is issued
(valid only when the DCE bit in MIM is set to 1).
Settings other than above are prohibited. If such
settings are made, correct operation is not guaranteed.
Note that setting the M_CKE pin low by the PCKE bit in
MIM is used to reduce the DDR-SDRAM power
consumption.
Rev. 1.00 Oct. 01, 2007 Page 422 of 1956
REJ09B0256-0100