SH7763 Datasheet, PDF (853/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Name
RMII transmit
data
RMII transmit
data
Transmit clock
Port
0
1
Receive clock
Transmit enable
MII/GMII
transmit data
GMII transmit
data
Transmit error
Receive data
valid
MII/GMII receive
data
GMII receive
data
Receive error
Carrier detection
Collision
detection
Management
data clock
Management
data I/O
RMII
management
data clock
Abbreviation
RMII0_TXD0
I/O
Function
Output 2-bit transmit data in RMII mode
RMII0_TXD1
Output 2-bit transmit data in RMII mode
ET1_TX-CLK Input
ET1_RX-CLK Input
ET1_TX-EN
Output
ET1_ETXD3 to Output
ET1_ETXD0
GET1_ETXD7 to Output
GET1_ETXD4
ET1_TX-ER
Output
ET1_RX-DV
Input
ET1_ERXD3 to Input
ET1_ERXD0
GET1_ERXD7 to Input
GET1_ERXD4
ET1_RX-ER
Input
ET1_CRS
ET1_COL
Input
Input
ET1_TX-EN, ET1_ETXD3 to
ET1_ETXD0, ET1_TX-ER timing
reference signal
ET1_RX-DV, ET1_ERXD3 to
ET1_ERXD0, ET1_RX-ER timing
reference signal
Indicates that transmit data is ready on
ET1_ETXD3 to ET1_ETXD0
4-bit MII transmit data or lower four bits of
GMII transmit data
Upper four bits of GMII transmit data
Notifies PHY-LSI of error during
transmission
Indicates that valid receive data is on
ET1_ERXD3 to ET1_ERXD0
4-bit MII receive data or lower four bits of
GMII receive data (MII and GMII)
Upper four bits of GMII receive data
Identifies error state occurred during data
reception
Carrier detection signal
Collision detection signal
ET1_MDC
ET1_MDIO
RMII1_MDC
Output
I/O
Output
Reference clock signal for information
transfer via ET1_MDIO
Bidirectional signal for exchange of
management information between STA
and PHY
Reference clock signal for information
transfer via RMII1_MDIO in RMII mode
Rev. 1.00 Oct. 01, 2007 Page 787 of 1956
REJ09B0256-0100