SH7763 Datasheet, PDF (416/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Bit
3 to 0
Initial
Bit Name Value R/W
IW[3:0]
1111 R/W
Description
Insert Wait Cycle
Specify the number of wait cycles to be inserted.
(Available only when the SRAM interface, byte control
SRAM interface, or burst ROM interface is selected.)
0000: No cycle inserted
0001: 1 cycle inserted
0010: 2 cycles inserted
0011: 3 cycles inserted
0100: 4 cycles inserted
0101: 5 cycles inserted
0110: 6 cycles inserted
0111: 7 cycles inserted
1000: 8 cycles inserted
1001: 9 cycles inserted
1010: 11 cycles inserted
1011: 13 cycles inserted
1100: 15 cycles inserted
1101: 17 cycles inserted
1110: 21 cycles inserted
1111: 25 cycles inserted
Note: IW[2:0] specify the number of wait cycles to be
inserted into read and write cycles when MPX
interface is selected.
IW[1:0] specify the number of wait cycles to be inserted
into first data.
00: 1 cycle inserted into read cycle and no cycle
inserted into write cycle
01: 1 cycle inserted into read cycle and 1 cycle inserted
into write cycle
10: 2 cycle inserted into read cycle and 2 cycle inserted
into write cycle
11: 3 cycle inserted into read cycle and 3 cycle inserted
into write cycle
IW2 specifies the number of wait cycle to be inserted
into second data or after.
0: No cycle inserted
1: 1 cycle inserted
IW3: Reserved
Rev. 1.00 Oct. 01, 2007 Page 350 of 1956
REJ09B0256-0100