SH7763 Datasheet, PDF (573/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(12) PCI Arbiter Bus Master Information Register (PCIBMIR)
In host bridge mode, this register records when the interrupt is invoked by PCIAINT.
When multiple interrupts occur, only the first source is registered.
When an interrupt is masked, the source is registered in corresponding bit (set to 1), however, an
interrupt occurs.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
REQ4 REQ3 REQ2 REQ1 REQ0
BME BME BME BME BME
Initial value: 0
0
0
0
0
0
0
0
0
0
0 —————
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: R R R R R R R R R R R R R R R R
Bit
31 to 5
4
3
2
1
0
Bit Name

Initial
Value
All 0
R/W
SH: R
PCI: R
REQ4BME Undefined SH: R
PCI: R
REQ3BME Undefined SH: R
PCI: R
REQ2BME Undefined SH: R
PCI: R
REQ1BME Undefined SH: R
PCI: R
REQ0BME Undefined SH: R
PCI: R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
REQ4 Error
An error occurs when the PCIC functions as a bus
master.
REQ3 Error
An error occurs when device 3 (REQ3) functions as a
bus master
REQ2 Error
An error occurs when device 2 (REQ2) functions as a
bus master
REQ1 Error
An error occurs when device 1 (REQ1) functions as a
bus master
REQ0 Error
An error occurs when device 0 (REQ0) functions as a
bus master
Rev. 1.00 Oct. 01, 2007 Page 507 of 1956
REJ09B0256-0100