SH7763 Datasheet, PDF (919/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.37 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0)
TSU_FWSL0 sets the processing method (enable or disable relay operation) of each frame in port
0 reception and port 0 to 1 relay operations. For multicast frames and frames whose destinations
are other than this LSI, the processing method in relay operations can be determined by referring
to the CAM evaluation results. (For details, refer to section 23.4.5, CAM Function.) This register
must not be written to once after relay operations have been enabled (after the FWEN0 bit in
TSU_FWEN0 or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0


 FW50 FW40 FW30 FW20 FW10 

 RMSA0 



Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R R R R
Bit
Bit Name
31 to 13 
12
FW50
11
FW40
10
FW30
Initial
Value
All 0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Sets the processing method when frames from port 0
are MAC control frames.
0: Frames are not relayed
1: Frames are relayed to port 1
R/W Sets the processing method when frames from port 0
are addressed to this LSI.
0: Frames are not relayed
1: Frames are relayed to port 1
R/W Sets the processing method when frames from port 0
are Broadcast frames.
0: Frames are not relayed
1: Frames are relayed to port 1
Rev. 1.00 Oct. 01, 2007 Page 853 of 1956
REJ09B0256-0100