SH7763 Datasheet, PDF (600/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(4) Accessing Internal Registers of this LSI
All internal registers, that is, PCIECR, PCI configuration registers, and PCI local registers are
accessible from the CPU.
4-byte, 2-byte, and byte transmission are supported.
(5) Endian
The PCIC of this LSI supports both the big endian and little endian formats. Since PCI local bus is
inherently little endian, the PCIC supports both byte swapping and non-byte swapping.
The endian format is specified by the setting of the TBS bit in the PCI control register (PCICR) at
a reset.
Note: In the following figures, “SH” means the SuperHyway bus of this LSI and “PCI” means
the PCI local bus. “MSByte” means the most significant byte and “LSByte” means the
least significant byte.
Rev. 1.00 Oct. 01, 2007 Page 534 of 1956
REJ09B0256-0100