|
SH7763 Datasheet, PDF (138/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
|
◁ |
Section 3 Instruction Set
Table 3.8 Branch Instructions
Instruction
BF
label
BF/S
label
BT
label
BT/S
label
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
label
Rn
label
Rn
@Rn
@Rn
Operation
Instruction Code
Privileged T Bit
When T = 0, disp à 2 + PC + 10001011dddddddd â
â
4 â PC
When T = 1, nop
Delayed branch; when T = 0, 10001111dddddddd â
â
disp à 2 + PC + 4 â PC
When T = 1, nop
When T = 1, disp à 2 + PC + 10001001dddddddd â
â
4 â PC
When T = 0, nop
Delayed branch; when T = 1, 10001101dddddddd â
â
disp à 2 + PC + 4 â PC
When T = 0, nop
Delayed branch, disp à 2 +
1010dddddddddddd â
â
PC + 4 â PC
Delayed branch, Rn + PC + 4 â 0000nnnn00100011 â
â
PC
Delayed branch, PC + 4 â PR, 1011dddddddddddd â
â
disp à 2 + PC + 4 â PC
Delayed branch, PC + 4 â PR, 0000nnnn00000011 â
â
Rn + PC + 4 â PC
Delayed branch, Rn â PC
0100nnnn00101011 â
â
Delayed branch, PC + 4 â PR, 0100nnnn00001011 â
â
Rn â PC
Delayed branch, PR â PC
0000000000001011 â
â
New
â
â
â
â
â
â
â
â
â
â
â
Table 3.9 System Control Instructions
Instruction
Operation
CLRMAC
0 â MACH, MACL
CLRS
0âS
CLRT
0âT
ICBI
@Rn Invalidates instruction cache
block indicated by virtual
address
LDC
Rm,SR Rm â SR
LDC
Rm,GBR Rm â GBR
LDC
Rm,VBR Rm â VBR
Instruction Code
Privileged T Bit
0000000000101000 â
â
0000000001001000 â
â
0000000000001000 â
0
0000nnnn11100011 

New
â
â
â
New
0100mmmm00001110 Privileged LSB â
0100mmmm00011110 â
â
â
0100mmmm00101110 Privileged â
â
Rev. 1.00 Oct. 01, 2007 Page 72 of 1956
REJ09B0256-0100
|
▷ |