SH7763 Datasheet, PDF (1805/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
Initial
Bit
Bit Name value R/W Description
2
PK2PUPR 1
R/W Controls pull-up of the PTK2 pin
0: PTK2 pin pull-up off
1: PTK2 pin pull-up on
1
PK1PUPR 1
R/W Controls pull-up of the PTK1 pin
0: PTK1 pin pull-up off
1: PTK1 pin pull-up on
0
PK0PUPR 1
R/W Controls pull-up of the PTK0 pin
0: PTK0 pin pull-up off
1: PTK0 pin pull-up on
40.2.34 Port L Pull-Up Control Register (PLPUPR)
PLPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTL7 to
PTL0, and when the pins of Port L are used by “other function”, pull-up control is performed for
the individual pins. The settings in this register are invalid for the pins specified to function as port
pins by PLCR.
Bit: 7
6
5
4
3
2
1
0
PL7PUPR PL6PUPR PL5PUPR PL4PUPR PL3PUPR PL2PUPR PL1PUPR PL0PUPR
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7
PL7PUPR 1
R/W Controls pull-up of the PTL7 pin
0: PTL7 pin pull-up off
1: PTL7 pin pull-up on
6
PL6PUPR 1
R/W Controls pull-up of the PTL6 pin
0: PTL6 pin pull-up off
1: PTL6 pin pull-up on
5
PL5PUPR 1
R/W Controls pull-up of the PTL5 pin
0: PTL5 pin pull-up off
1: PTL5 pin pull-up on
Rev. 1.00 Oct. 01, 2007 Page 1739 of 1956
REJ09B0256-0100