SH7763 Datasheet, PDF (1079/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.7 Transmit/Receive Packet Counter Registers 0, 1 (STIPCR0, STIPCR1)
The number of packets of stream data that have been transmitted or received is set in STIPCR. At
reception, the number of packets in this register is incremented after the last byte in the packet has
been transferred to memory. At transmission, the number of packets is incremented after the last
data in the packet has been sent from the ST_D7 to ST_D0 pins. In addition, the numbers of short
packets and long packets that have been received are also set in this register.
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SC[3:0]
LC[3:0]
− −−
PC[20:16]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PC[15:0]
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Initial
Bit
Bit Name Value
31 to 28 SC[3:0] All 0
27 to 24 LC[3:0] All 0
23 to 21 
All 0
20 to 0 PC[20:0] All 0
R/W Description
R
Number of Received Short Packets
Cleared to 0 at a reset.
R
Number of Received Long Packets
Cleared to 0 at a reset.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Number of Transmitted/Received Packets
Cleared to 0 when a transmit packet count interrupt or
receive packet count interrupt occurs, or at a reset.
Rev. 1.00 Oct. 01, 2007 Page 1013 of 1956
REJ09B0256-0100