SH7763 Datasheet, PDF (1526/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3 Register Description
Table 35.2 shows the USBH register configuration. Table 35.3 shows the register state in each
operating mode. Other than the ConfigulationControl register, all registers conform to the
OpenHCIs specification. For details, refer to the OpenHCI Rev1.0. The Configuration Control
register is only for this LSI.
Table 35.2 Register Configuration
Register Name
HcRevision register
HcControl register
HcCommandStatus register
HcInterruptStatus register
HcInterruptEnable register
HcInterruptDisable register
HcHCCA register
HcPeriodCurrentED register
HcControlHeadED register
HcControlCurrentED register
HcBulkHeadED register
HcBulkCurrentED register
HcDoneHead register
HcFmInterval register
HcFmRemaining register
HcFmNumber register
HcPeriodicStart register
HcLSThreshold register
HcRhDescriptorA register
HcRhDescriptorB register
Abbreviation R/W
USBHR
R
USBHC
R/W
USBHCS R/W
USBHIS
R/W
USBHIE
R/W
USBHID
R/W
USBHHCCA R/W
USBHPCED R/W
USBHCHED R/W
USBHCCED R/W
USBHBHED R/W
USBHBCED R/W
USBHDHED R/W
USBHFI
R/W
USBHFR
R
USBHFN
R
USBHPS
R/W
USBHLST R/W
USBHRDA R/W
USBHRDB R/W
Area P4
Address*
H'FFEC 8000
H'FFEC 8004
H'FFEC 8008
H'FFEC 800C
H'FFEC 8010
H'FFEC 8014
H'FFEC 8018
H'FFEC 801C
H'FFEC 8020
H'FFEC 8024
H'FFEC 8028
H'FFEC 802C
H'FFEC 8030
H'FFEC 8034
H'FFEC 8038
H'FFEC 803C
H'FFEC 8040
H'FFEC 8044
H'FFEC 8048
H'FFEC 804C
Area 7
Address*
H'1FEC 8000
H'1FEC 8004
H'1FEC 8008
H'1FEC 800C
H'1FEC 8010
H'1FEC 8014
H'1FEC 8018
H'1FEC 801C
H'1FEC 8020
H'1FEC 8024
H'1FEC 8028
H'1FEC 802C
H'1FEC 8030
H'1FEC 8034
H'1FEC 8038
H'1FEC 803C
H'1FEC 8040
H'1FEC 8044
H'1FEC 8048
H'1FEC 804C
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Rev. 1.00 Oct. 01, 2007 Page 1460 of 1956
REJ09B0256-0100