SH7763 Datasheet, PDF (1192/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.1 Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data.
The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting
with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to SCFRDR, automatically.
SCRSR cannot be directly read from and written to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value:        
R/W:        
28.3.2 Receive FIFO Data Register (SCFRDR)
SCFRDR is an 8-bit FIFO register of 16 stages that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until SCFRDR is full (16 data
bytes).
SCFRDR is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in SCFRDR, an undefined value will be
returned. When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is undefined at a power-on reset or a manual reset.
Bit: 7
6
5
4
3
2
1
0
Initial value: _{       }
R/W: R R R R R R R R
Rev. 1.00 Oct. 01, 2007 Page 1126 of 1956
REJ09B0256-0100