SH7763 Datasheet, PDF (883/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.5 PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI internal
registers via the GMII/MII/RMII.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0











 MDI MDO MMD MDC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 4 
All 0
R
3
MDI
Undefined R
2
MDO
0
R/W
1
MMD
0
R/W
0
MDC
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
GMII/MII/RMII Management Data-In
Indicates the level of the ET_MDIO pin.
GMII/MII/RMII Management Data-Out
Outputs the value set in this bit from the ET_MDIO pin
when the MMD bit is 1.
GMII/MII/RMII Management Mode
Specifies the data read/write direction with respect to
the GMII/MII/RMII.
0: Read direction is specified
1: Write direction is specified
GMII/MII/RMII Management Data Clock
Outputs the value set in this bit from the ET_MDC pin
and supplies the GMII/MII/RMII with the management
data clock. For the method of accessing the
GMII/MII/RMII registers, see section 23.5.4, Accessing
MII Registers.
Rev. 1.00 Oct. 01, 2007 Page 817 of 1956
REJ09B0256-0100