SH7763 Datasheet, PDF (1144/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
7
ER
0
R/W*¹ Receive Error
Indicates that a framing error or parity error occurred
during reception. The ER flag is not affected and retains
its previous state when the RE bit in SCSCR is cleared
to 0. When a receive error occurs, the receive data is
still transferred to SCFRDR, and reception continues.
The FER and PER bits in SCFSR can be used to
determine whether there is a receive error in the
readout data from SCFRDR.
0: No framing error or parity error occurred during
reception
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ER after reading ER = 1
1: A framing error or parity error occurred during
reception
[Setting conditions]
• When the SCIF checks whether the stop bit at the
end of the receive data is 1 when reception ends,
and the stop bit is 0*²
• When, in reception, the number of 1-bits in the
receive data plus the parity bit does not match the
parity setting (even or odd) specified by the O/E bit
in SCSMR
6
TEND
1
R/W*¹ Transmit End
Indicates that transmission has been ended without
valid data in SCFTDR after transmission of the last bit
of the transmit character.
0: Transmission is in progress
[Clearing conditions]
• When transmit data is written to SCFTDR, and 0 is
written to TEND after reading TEND = 1
• When data is written to SCFTDR by the DMAC
1: Transmission has been ended
[Setting conditions]
• Power-on reset or manual reset
• When the TE bit in SCSCR is 0
• When there is no transmit data in SCFTDR after
transmission of the last bit of a 1-byte serial transmit
character
Rev. 1.00 Oct. 01, 2007 Page 1078 of 1956
REJ09B0256-0100