SH7763 Datasheet, PDF (1796/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.25 Port J Data Register (PJDR)
PJDR is an 8-bit readable/writable register that stores port J data.
Bit: 7
6
5
4
3
2
1
0
PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT PJ0DT
Initial value: Pin state Pin state Pin state Pin state Pin state Pin state Pin state Pin state
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7
PJ7DT
Pin state R/W Each of these bits stores output data for the
6
PJ6DT
Pin state R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
5
PJ5DT
Pin state R/W _{this register will be read for a pin configured as a}
4
PJ4DT
Pin state R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
3
PJ3DT
Pin state R/W _{general input port.}
2
PJ2DT
Pin state R/W
1
PJ1DT
Pin state R/W
0
PJ0DT
Pin state R/W
Rev. 1.00 Oct. 01, 2007 Page 1730 of 1956
REJ09B0256-0100