SH7763 Datasheet, PDF (1066/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3 Register Descriptions
Table 25.2 shows the STIF register configuration. Table 25.3 shows the register states in each
operating mode.
Table 25.2 Register Configuration
Register Name
Abbrevia-
tion
R/W
Mode register 0
STIMDR0 R/W
Control register 0
STICR0 R/W
Interrupt status register 0
STIISR0 R/W
Interrupt enable register 0
STIIER0 R/W
Time stamp counter register 0
STITSC0 R/W
Transmit/receive packet count
register 0
STIPNR0 R/W
Transmit/receive packet counter
register 0
STIPCR0 R/W
Transmit/receive FIFO data register 0 STIFIFO0 R/W
Mode register 1
STIMDR1 R/W
Control register 1
STICR1 R/W
Interrupt status register 1
STIISR1 R/W
Interrupt enable register 1
STIIER1 R/W
Time stamp counter register 1
STITSC1 R/W
Transmit/receive packet count
register 1
STIPNR1 R/W
Transmit/receive packet counter
register 1
STIPCR1 R/W
Transmit/receive FIFO data register 1 STIFIFO1 R/W
Area P4
Address
Area 7
Address
Access
Size
H'FFEE 0000 H'1FEE 0000 32
H'FFEE 0004 H'1FEE 0004 32
H'FFEE 0008 H'1FEE 0008 32
H'FFEE 000C H'1FEE 000C 32
H'FFEE 0010 H'1FEE 0010 32
H'FFEE 0018 H'1FEE 0018 32
H'FFEE 0014 H'1FEE 0014 32
H'FFEE 0400 H'1FEE 0400 32
H'FFEE 8000 H'1FEE 8000 32
H'FFEE 8004 H'1FEE 8004 32
H'FFEE 8008 H'1FEE 8008 32
H'FFEE 800C H'1FEE 800C 32
H'FFEE 8010 H'1FEE 8010 32
H'FFEE 8018 H'1FEE 8018 32
H'FFEE 8014 H'1FEE 8014 32
H'FFEE 8400 H'1FEE 8400 32
Rev. 1.00 Oct. 01, 2007 Page 1000 of 1956
REJ09B0256-0100