SH7763 Datasheet, PDF (1613/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Bit Bit name
1
ASCE
0

Section 36 USB Function Controller (USBF)
Initial value R/W Description
0
R/W Automatic Stall Clear Enable
When this bit is set to 1, the stall handshake is
returned to the host and the stall setting bit
(EPSTLR/EPXSTL) of the returned endpoint is
automatically cleared. Control in a unit of endpoint is
disabled as this bit is common for all endpoints. When
this bit is set to 0, be sure to clear the stall setting bit
of each endpoint by using software.
This bit should be set to 1 before each stall bit in
EPSTL is set to 1.
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1547 of 1956
REJ09B0256-0100