SH7763 Datasheet, PDF (112/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
Initial
Bit
Bit Name Value R/W
27 to 16 —
All 0 R
15
FD
0
R/W
14 to 10 —
All 0 R
9
M
8
Q
7 to 4 IMASK
0
R/W
0
R/W
All 1 R/W
3, 2
—
1
S
0
T
All 0 R
0
R/W
0
R/W
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
FPU Disable Bit
When this bit is set to 1 and an FPU instruction is not in
a delay slot, a general FPU disable exception occurs.
When this bit is set to 1 and an FPU instruction is in a
delay slot, a slot FPU disable exception occurs. (FPU
instructions: H'F*** instructions and LDS (.L)/STS(.L)
instructions using FPUL/FPSCR)
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
M Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level Bits
An interrupt whose priority is equal to or less than the
value of the IMASK bits is masked. It can be chosen by
CPU operation mode register (CPUOPM) whether the
level of IMASK is changed to accept an interrupt or not
when an interrupt is occurred. For details, see appendix
A, CPU Operation Mode Register (CPUOPM).
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
S Bit
Used by the MAC instruction.
T Bit
Indicates true/false condition, carry/borrow, or
overflow/underflow.
For details, see section 3, Instruction Set.
Rev. 1.00 Oct. 01, 2007 Page 46 of 1956
REJ09B0256-0100