SH7763 Datasheet, PDF (1855/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
3. When the operand access (address only) is specified as the match condition:
The address of the instruction immediately after the instruction which has satisfied the break
conditions is saved in the SPC. The instruction which has satisfied the match conditions are
executed, then a break occurs before the next instruction. However, if the conditions are
satisfied for the delayed slot, the address of the branch destination is saved in the SPC.
4. When the operand access (address and data) is specified as the match condition:
If the data value is added to the match conditions, the instruction which has satisfied the match
conditions is executed. A user break occurs before executing an instruction that is one through
six instructions after the instruction which has satisfied the match conditions. The address of
the instruction is saved in the SPC; thus, it is impossible to identify exactly where a break will
occur. If the conditions are satisfied for the delayed slot instruction, the address of the branch
destination is saved in the SPC. If a branch instruction follows the instruction which has
satisfied the match conditions, a break may occur after the delayed instruction and delayed slot
are executed. In this case, the address of the branch destination is also saved in the SPC.
41.4 User Break Debugging Support Function
By using the user break debugging support function, the branch destination address can be
modified when the CPU accepts the user break request. Specifically, setting the UBDE bit of
break control register CBCR to 1 allows branching to the address indicated by DBR instead of
branching to the address indicated by the [VBR + offset]. Figure 41.2 shows the flowchart of the
user break debugging support function.
Rev. 1.00 Oct. 01, 2007 Page 1789 of 1956
REJ09B0256-0100