SH7763 Datasheet, PDF (319/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.3.6 Interrupt mask register 1 (INTMSK1)
INTMSK1 is 32-bit readable and writable with conditions registers that control mask settings for
each interrupt request. To clear the mask settings for interrupts, write 1 to the corresponding bits
in INTMSKCLR1. Writing 0 to bits in INTMSK1 is invalid.
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− ^{IM10 IM11} − − − − − − − − − − − − −
Initial value:
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R R R R R R R R R R
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−− −− −− −−− −−− −− − −
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
Initial
Bit
Bit Name Value
31
IM10
1
30
IM11
1
29 to 24 
All 1
23 to 0 
All 0
R/W Description
R/W Sets masking of IRL3 to
IRL0 interrupt requests
when IRQ3/IRL3 to
IRQ0/IRL0 are encoded
interrupt input.
[When reading]
0: Interrupts are accepted
1: Interrupts are masked
[When writing]
R/W Sets masking of IRQ7/IRL7 0: Invalid
to IRQ4/IRL4 interrupt
1: Interrupts are masked
requests when IRL [7:4] are
encoded interrupt input.
R
Reserved
These bits are always read as 1. The write value should
always be 1.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 253 of 1956
REJ09B0256-0100