SH7763 Datasheet, PDF (250/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
6.7.6 Notes on Using 32-Bit Address Extended Mode
When using 32-bit address extended mode, note that the items described in this section are
extended or changed as follows.
PASCR: The SE bit is added in bit 31 in the control register (PASCR). The bits 6 to 0 of the UB
in the PASCR are invalid (Note that the bit 7 of the UB is still valid). When writing to the P1 or
P2 area, the UB bit in the PMB controls whether a buffered write is performed or not. When the
MMU is enabled, the UB bit in the TLB controls writing to the P0, P3, or U0 area. When the
MMU is disabled, writing to the P0, P3, or U0 area is always performed as a buffered write.
Bit
Bit Name
31
SE
30 to 8 
7 to 0 UB
Initial
Value
0
All 0
All 0
R/W Description
R/W 0: 29-bit address mode
1: 32-bit address extended mode
R
Reserved
For details on reading from or writing to these bits,
see description in General Precautions on Handling
of Product.
R/W Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or
in the cache write-through mode, these bits specify
whether the CPU waits for the end of writing for each
area.
0: The CPU does not wait for the end of writing
1: The CPU stalls and waits for the end of writing
UB[7]: Corresponding to the control register area
UB[6:0]: These bits are invalid in 32-bit address
extended mode.
ITLB: The PPN field in the ITLB is extended to bits 31 to 10.
UTLB: The PPN field in the UTLB is extended to bits 31 to 10. The same UB bit as that in the
PMB is added in each entry of the UTLB.
Rev. 1.00 Oct. 01, 2007 Page 184 of 1956
REJ09B0256-0100