SH7763 Datasheet, PDF (484/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Initial
Bit
Bit Name Value
45

0
44
PCKE
0
43 to 35 
All 0
34
SELFS 0
33
RMODE 0
32 to 29 
All 0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Power Down
When the DDR-SDRAM is not accessed (in the idle
state or bank active state), this bit sets the CKE pin low
and the power-down mode is entered. When this bit is
set to 1, the power-down mode is entered to reduce the
DDR-DSRAM power consumption. For details, see
section 12.5.5, Power-Down Modes. Note that the
setting for enabling the CKE pin by the SMS bit in SCR
is used for DDR-SDRAM initialization.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Self-Refresh Decision
Decides whether the DDR-SDRAM is in the self-refresh
state. When this bit is set to 1, the DDR-SDRAM is in
the self-refresh state. When this bit is cleared to 0, the
DDR-SDRAM is not in the self-refresh state.
R/W Refresh Mode Select
Specifies whether auto-refresh mode or self-refresh
mode is set to the DDR-SDRAM. This bit is valid only
when the DRE bit in MIM is set to 1.
0: Auto-refresh mode
1: Self-refresh mode
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 418 of 1956
REJ09B0256-0100