SH7763 Datasheet, PDF (510/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
(MCLK)
MCLK
CKE
Command
MA9-0
MA13-11
MA10
BA1-0
MCS
MRAS
MCAS
MWE
MDQS
MDA
MDQM
T0 T1 T2 T3 T4
PREALL
t_RP (SRP = 1)
ACT
Row
Row
Bank
Hi-Z
Hi-Z
Figure 12.11 Basic DDRIF Timing (Precharge all Banks (PREALL) to Bank Activate
(ACT))
Rev. 1.00 Oct. 01, 2007 Page 444 of 1956
REJ09B0256-0100