SH7763 Datasheet, PDF (987/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Bit
Bit Name
15 to 11 
10
DLCCE
9
CDCE
8
TROCE
7
RMAFCE
6
CEEFCE
5
CELFCE
Initial
Value
All 0
0
0
0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W DLC Bit Copy Directive
0: Reflects the DLC bit status in the TFE bit of the
transmit descriptor
1: Occurrence of the corresponding source is not
reflected in the TFE bit of the transmit descriptor
R/W CD Bit Copy Directive
0: Reflects the CD bit status in the TFE bit of the
transmit descriptor
1: Occurrence of the corresponding source is not
reflected in the TFE bit of the transmit descriptor
R/W TRO Bit Copy Directive
0: Reflects the TRO bit status in the TFE bit of the
transmit descriptor
1: Occurrence of the corresponding source is not
reflected in the TFE bit of the transmit descriptor
R/W RMAF Bit Copy Directive
0: Reflects the RMAF bit status in the RFE bit of the
receive descriptor
1: Occurrence of the corresponding source is not
reflected in the RFE bit of the receive descriptor
R/W CEEF Bit Copy Directive
0: Reflects the CEEF bit status in the RFE bit of the
receive descriptor
1: Occurrence of the corresponding source is not
reflected in the RFE bit of the receive descriptor
R/W CELF Bit Copy Directive
0: Reflects the CELF bit status in the RFE bit of the
receive descriptor
1: Occurrence of the corresponding source is not
reflected in the RFE bit of the receive descriptor
Rev. 1.00 Oct. 01, 2007 Page 921 of 1956
REJ09B0256-0100