SH7763 Datasheet, PDF (1106/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.3.7 Master Interrupt Enable Register (ICMIER)
BIt:
Initial value:
R/W:
7
6
5
4
3
2
1
0
− MNRE MALE MSTE MDEE MDTE MDRE MATE
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
7
—
0
R
Reserved
The write value should always be 0.
6
MNRE
0
R/W Master Nack Received Interrupt Enable
0: Disables the MNR interrupt.
1: Enables the MNR interrupt.
5
MALE
0
R/W Master Arbitration Lost Interrupt Enable
0: Disables the MAL interrupt.
1: Enables the MAL interrupt.
4
MSTE
0
R/W Master Stop Transmitted Interrupt Enable
0: Disables the MST interrupt.
1: Enables the MST interrupt.
3
MDEE
0
R/W Master Data Empty Interrupt Enable
0: Disables the MDE interrupt.
1: Enables the MDE interrupt.
2
MDTE
0
R/W Master Data Transmitted Interrupt Enable
0: Disables the MDT interrupt.
1: Enables the MDT interrupt.
1
MDRE
0
R/W Master Data Received Interrupt Enable
0: Disables the MDR interrupt.
1: Enables the MDR interrupt.
0
MATE
0
R/W Master Address Transmitted Interrupt Enable
0: Disables the MAT interrupt.
1: Enables the MAT interrupt.
Rev. 1.00 Oct. 01, 2007 Page 1040 of 1956
REJ09B0256-0100