SH7763 Datasheet, PDF (1167/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
(5) Serial Data Reception (Asynchronous Mode)
Figure 27.12 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read ER, DR, BRK flags in
SCFSR and ORER
flag in SCLSR
ER, DR, BRK or ORER = 1?
No
[1]
Yes
Error handling
[1] Receive error handling and
break detection:
Read the DR, ER, and BRK
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the
SCIF_RXD pin.
Read RDF flag in SCFSR
[2]
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
All data received?
[3]
Yes
Clear RE bit in SCSCR to 0
End of reception
[2] SCIF status check and receive
data read:
Read SCFSR and check that
RDF = 1, then read the receive
data in SCFRDR, read 1 from
the RDF flag, and then clear
the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can also be identified by
an RXI interrupt.
[3] Serial reception continuation
procedure:
To continue serial reception,
read at least the receive
trigger set number of receive
data bytes from SCFRDR,
read 1 from the RDF flag, then
clear the RDF flag to 0. The
number of receive data bytes
in SCFRDR can be
ascertained by reading from
SCRFDR.
Figure 27.12 Sample Serial Reception Flowchart (1)
Rev. 1.00 Oct. 01, 2007 Page 1101 of 1956
REJ09B0256-0100