SH7763 Datasheet, PDF (1258/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.1 Mode Register (SIMDR)
SIMDR is a 16-bit readable/writable register that sets the SIOF operating mode.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRMD[1:0]
SYN
CAT
REDG
FL[3:0]
TXDIZ RCIM
SYN
CAC
SYN
CDL
—
—
—
—
Initial value: 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
Initial
Bit
Bit Name Value R/W
15, 14 TRMD[1:0] 10
R/W
13
SYNCAT 0
R/W
12
REDG
0
R/W
11 to 8 FL[3:0]
0000 R/W
Description
Transfer Mode
Select transfer mode as shown in table 29.4.
00: Slave mode 1
01: Slave mode 2
10: Master mode 1
11: Master mode 2
SIOF_SYNC Pin Valid Timing
Indicates the position of the SIOF_SYNC signal to be
output as a synchronization pulse.
0: At the start-bit data of frame
1: At the last-bit data of slot
Receive Data Sampling Edge
0: The SIOF_RXD signal is sampled at the falling edge
of SIOF_SCK
1: The SIOF_RXD signal is sampled at the rising edge
of SIOF_SCK
Note: The timing to transmit the SIOF_TXD signal is at
the opposite edge of the timing that samples the
SIOF_RXD. This bit is valid only in master
mode.
Frame Length
Specifies the flame length and transfer data format. For
details, refer to table 29.7.
Rev. 1.00 Oct. 01, 2007 Page 1192 of 1956
REJ09B0256-0100