SH7763 Datasheet, PDF (322/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value R/W Description
15
IM115
0
14
IM114
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LLLL (H'0).
R/W Sets masking of an
interrupt request when
IRL [7:4] = LLLH (H'1).
[When reading]
0: Interrupts are accepted
1: Interrupts are masked
[When writing]
0: Invalid
13
IM113
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LLHL (H'2).
1: Interrupts are masked
12
IM112
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LLHH (H'3).
11
IM111
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LHLL (H'4).
10
IM110
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LHLH (H'5).
9
IM109
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LHHL (H'6).
8
IM108
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = LHHH (H'7).
7
IM107
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = HLLL (H'8).
6
IM106
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = HLLH (H'9).
5
IM105
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = HLHL (H'A).
4
IM104
0
R/W Sets masking of an
interrupt request when
IRL [7:4] = HLHH (H'B).
Rev. 1.00 Oct. 01, 2007 Page 256 of 1956
REJ09B0256-0100