SH7763 Datasheet, PDF (1076/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Bit
7 to 5
Initial
Bit Name Value

All 0
4
ROVFE 0
3 to 1 
All 0
0
TSTOE 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive FIFO Overflow Interrupt Enable
0: Receive FIFO overflow interrupt is disabled
1: Receive FIFO overflow interrupt is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Time Stamp Counter Overflow Interrupt Enable
0: Time stamp counter overflow interrupt is disabled
1: Time stamp counter overflow interrupt is enabled
Rev. 1.00 Oct. 01, 2007 Page 1010 of 1956
REJ09B0256-0100