SH7763 Datasheet, PDF (413/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W Description
27

26 to 24 ADH
23

22 to 20 RDS
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
111
R/W Address Hold Cycle
Specify the number of cycles to be inserted to ensure
the address hold time to the CSn negation. However,
setting to over one cycle, one cycle decremented from
the setting value when RD strobe cycle in read access
or WE strobe cycle in write access is set to over 1
cycle. (Available only when the SRAM interface, byte
control SRAM interface, or burst ROM interface is
selected.)
Note that, it will be no inserted cycle when setting to 0
for inserted wait cycle and setting to 0 for RD strobe
hold wait in read access or WE strobe hold wait in write
access.
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
111
R/W RD Setup Cycle (CSn Assert–RD Assert Delay Cycle)
Specify the number of cycles to be inserted to ensure
the RD setup time to the T1. (Available only when the
SRAM interface, byte control SRAM interface, or burst
ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Rev. 1.00 Oct. 01, 2007 Page 347 of 1956
REJ09B0256-0100