SH7763 Datasheet, PDF (1607/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.32 Endpoint Stall Register 0 (EPSTL0)
EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake
to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared
automatically on reception of 8 byte command data for which decoding is performed by the
function and the EP0 STL bit is cleared. When the SETUPTS flag bit in the IFR0 register is set to
1, a write of the EP0 STL bit to 1 is ignored. For detailed operation, see section 36.8, Stall
Operations.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
EP3 EP2 EP1 EP0
STL STL STL STL
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit Bit Name
31 to 8 
7 to 4 
3
EP3 STL
2
EP2 STL
1
EP1 STL
0
EP0 STL
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
All 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
0
R/W EP3 Stall
Sets EP3 stall
0
R/W EP2 Stall
Sets EP2 stall
0
R/W EP1 Stall
Sets EP1 stall
0
R/W EP0 Stall
Sets EP0 stall
Rev. 1.00 Oct. 01, 2007 Page 1541 of 1956
REJ09B0256-0100