SH7763 Datasheet, PDF (1286/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
(1) Transmit/Receive Timing
The SIOF_TXD transmit timing and SIOF_RXD receive timing relative to the SIOF_SCK can be
set as the sampling timing in the following two ways. The transmit/receive timing is set using the
REDG bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 29.4 shows the transmit/receive timing.
(a) Falling-edge sampling REDG = 0
SIOF_SCK
(a) Rising-edge sampling REDG = 1
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
Receive timing
Transmit timing
SIOF_SYNC
SIOF_TXD
SIOF_RXD
Receive timing
Transmit timing
Figure 29.4 SIOF Transmit/Receive Timing
29.4.3 Transfer Data Format
The SIOF performs the following transfer.
• Transmit/receive data: Transfer of 8-bit data/16-bit data/16-bit stereo data
• Control data: Transfer of 16-bit data (uses the specific register as interface)
(1) Transfer Mode
The SIOF supports the following four transfer modes as listed in table 29.6. The transfer mode can
be specified by the bits TRMD[1:0] in SIMDR.
Rev. 1.00 Oct. 01, 2007 Page 1220 of 1956
REJ09B0256-0100