SH7763 Datasheet, PDF (632/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
• Active levels for both the DMA transfer request acceptance signal (DACKn) and DMA
transfer end signal (TENDn) can be set. (n = 0 to 3)
Figure 14.1 shows the block diagram of the DMAC.
On-chip memory
On-chip
peripheral
module
Peripheral
bus controller
DMA transfer request signal
DMA transfer end signal
Interrupt controller
DMINT0 to DMINT5
DMAE
DREQ0 to DREQ3
DACK0 to DACK3
TEND0 to TEND3
External ROM
External RAM
External I/O
Local bus state
controller
DDR-SDRAM
interface
PCI controller
DMAC channels 0 to 5
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus
interface
SARm
DARm
TCRm
CHCRm
DMAOR0
DMARS0-2
SARBn
DARBn
TCRBn
[Legend]
CHCRm:
DARBn:
DARm:
DMAE:
DMAOR :
DMA channel control register
DMA destination address register B
DMA destination address register
DMA Address error interrupt request
DMA operation register
DMARS0 to
DMARS2: DMA extended resource selectors 0 to 2
DMINTm: DMA transfer end/half-end interrupt request from channel m*
SARBn: DMA source address register B
SARm:
DMA source address register
TCRBn: DMA transfer count register B
TCRm:
DMA transfer count register
m:
n:
Note:
0,1,2,3,4,5 for channels 0 to 5
0,1,2,3 for channels 0 to 5
* The half-end interrupt request is available in channels 0 to 3.
Figure 14.1 Block Diagram of DMAC
Rev. 1.00 Oct. 01, 2007 Page 566 of 1956
REJ09B0256-0100