SH7763 Datasheet, PDF (313/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit
Bit Name Value
R/W Description
25
NMIB
0
R/W NMI Block Mode
Selects whether an NMI interrupt is held until the BL bit
in SR is cleared to 0 or detected immediately when the
BL bit in SR of the CPU is set to 1.
0: An NMI interrupt is held when the BL bit in SR is set
to 1 (initial value)
1: An NMI interrupt is not held when the BL bit in SR is
set to 1
Note: If interrupts are accepted with the BL bit in SR set
to 1, previous exception information (SSR, SPC,
SGR, and INTEVT) is lost.
24
NMIE
0
R/W NMI Edge Select
Selects whether an interrupt request signal to the NMI
pin is detected at the rising edge or the falling edge.
0: An interrupt request is detected at the falling edge of
NMI input (initial value)
1: An interrupt request is detected at the rising edge of
NMI input
23
IRLM0
0
R/W IRL Pin Mode 0
Selects whether IRQ3/IRL3 to IRQ0/IRL0 are used as
the 4-bit encoded interrupt requests or as four
independent interrupts.
0: IRQ3/IRL3 to IRQ0/IRL0 are used as the 4-bit level-
encoded interrupt requests (IRL [3:0] interrupt; initial
value)
1: IRQ3/IRL3 to IRQ0/IRL0 are used as four
independent interrupt requests (IRQ [n] interrupt; n
= 3 to 0)
Note: The level-encoded IRL interrupt is not detected
unless the pin levels sampled at every bus
clock cycle remain unchanged for four
consecutive cycles.
Rev. 1.00 Oct. 01, 2007 Page 247 of 1956
REJ09B0256-0100