SH7763 Datasheet, PDF (637/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
Table 14.3 State of Registers in Each Operating Mode
Channel Abbreviation
0
SAR0
DAR0
TCR0
CHCR0
1
SAR1
DAR1
TCR1
CHCR1
2
SAR2
DAR2
TCR2
CHCR2
3
SAR3
DAR3
TCR3
CHCR3
0 to 5 DMAOR
4
SAR4
DAR4
TCR4
CHCR4
5
SAR5
DAR5
TCR5
CHCR5
0
SARB0
DARB0
TCRB0
Power-on Reset
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000
H'0000
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000
Undefined
Undefined
Undefined
Manual Reset Sleep
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
H'0000
Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
H'4000 0000 Retained
Undefined
Retained
Undefined
Retained
Undefined
Retained
Stand by
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Oct. 01, 2007 Page 571 of 1956
REJ09B0256-0100