SH7763 Datasheet, PDF (569/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Bit
12
11
10 to 4
Initial
Bit Name Value
TBTOI
0
MBTOI 0

All 0
R/W
Description
SH: R/WC Target Bus Time-Out Interrupt
PCI: R
An interrupt is detected when the TRDY or STOP
signal is not asserted within 16 clock cycles on the
first data transfer.
An interrupt is detected when the TRDY or STOP
signal is not asserted within eight clock cycles during
the data transfer subsequent to the 2nd.
0: Target bus time-out interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target bus time-out interrupt occurs
[Set condition]
When a target bus time-out interrupt occurs.
SH: R/WC Master Bus Time-Out Interrupt
PCI: R
An interrupt is detected when the IRDY signal is not
asserted within 8 clock cycles.
0: Master bus time-out interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master bus time-out interrupt occurs
[Set condition]
When a master bus time-out interrupt occurs.
SH: R
Reserved
PCI: R
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 503 of 1956
REJ09B0256-0100