SH7763 Datasheet, PDF (1522/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
34.5 Usage Note
34.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation
If an overflow occurs during receive DMA operation, the module must be reactivated.
The receive buffer of SSI has 32-bit common register both left channel and right channel. If an
overflow occurs under the condition of control register (SSICR) data-word length (DWL2 to
DWL0) is 32-bit and system-word length (SWL2 to SWL0) is 32-bit, SSI has received the data at
right channel that should be received at left channel.
If an overflow occurs through an overflow error interrupt or overflow error status flag (the OIRQ
bit in SSISR), disable the DMA transfer of the SSI to halt its operation by writing 0 to the EN bit
and DMEN bit in SSICR (then terminate the DMA setting). And clear the overflow status flag by
writing 0 to the OIRQ bit, set the DMA again and transfer restart.
34.5.2 Restrictions for Operation in Slave Mode
To terminate data transfer while this LSI is used in slave mode, clear the EN bit in SSICR to 0 to
terminate data transfer before the word select signal supply is stopped.
In slave mode, data transfer is terminated if the EN bit (settings for terminating data transfer) is
cleared and the falling edge of the word select signal (SSI_WS) is detected. If the word select
signal supply is stopped before EN bit clear, the falling edge of the word select signal cannot be
detected, and thereby data transfer is not terminated properly.
Rev. 1.00 Oct. 01, 2007 Page 1456 of 1956
REJ09B0256-0100