SH7763 Datasheet, PDF (677/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
CLKOUT
Bus cycle
DREQ
(Rising edge)
DRAK
(Low-active)
DACK
(Low-active)
CPU
Burst acceptance
DMAC
: Non-sensitive period
DMAC
Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CLKOUT
Bus cycle
DREQ
(Overrun 0,
Low-level)
DRAK
(Low-active)
DACK
(Low-active)
CPU
1st acceptance
DMAC
2nd acceptance
Acceptance started
CLKOUT
Bus cycle
DREQ
(Overrun 1,
Low-level)
DRAK
(Low-active)
DACK
(Low-active)
CPU
1st acceptance
DMAC
2nd acceptance
: Non-sensitive period
Acceptance
started
DMAC
3rd acceptance
Acceptance
started
Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 1.00 Oct. 01, 2007 Page 611 of 1956
REJ09B0256-0100