SH7763 Datasheet, PDF (474/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.5.11 Cooperation between Master and Slave
To enable system resources to be controlled in a harmonious fashion by master and slave, their
respective roles must be clearly defined.
When designing an application system that includes this LSI, all control, including initialization,
and low power consumption control, are supposed to be carried out by this LSI.
In a power-on reset, this LSI will not accept bus requests from the slave until the BREQ enable bit
(BCR.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use,
write 1 to the BREQ enable bit only after this LSI has performed the initialization.
Rev. 1.00 Oct. 01, 2007 Page 408 of 1956
REJ09B0256-0100