SH7763 Datasheet, PDF (907/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.29 TSU Counter Reset Register (TSU_CTRST)
TSU_CTRST clears the transmit, receive, and relay frame counters to 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






 CTRST 







Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31 to 9 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
CTRST 0
R/W TSU Counter Reset
When 1 is written to this bit, the values of registers
TXNLCR0/TXNLCR1, TXALCR0/TXALCR1,
RXNLCR0/RXNLCR1, RXALCR0/RXALCR1,
FWNLCR0/FWNLCR1, and FWALCR0/FWALCR1 are
cleared to 0. Writing 0 does not affect this bit. This bit is
always read as 0.
7 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 841 of 1956
REJ09B0256-0100