SH7763 Datasheet, PDF (1742/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 39 D/A Converter (DAC)
39.3.2 D/A Control Register (DACR)
The DACR register is an 8-bit readable/writable register that controls D/A converter operation.
The DACR is initialized to H'3F at reset. Note that the DACR is not initialized in software
standby, module standby, or hardware standby mode.
Bit: 7
6
5
4
3
2
1
0
DAOE1 DAOE0 —
—
—
—
—
—
Initial value: 0
0
1
1
1
1
1
1
R/W: R/W R/W R
R
R
R
R
R
Initial
Bit Bit Name Value
7
DAOE1 0
6
DAOE0 0
5 to 0 
All 1
R/W
R/W
R/W
R
Description
Controls D/A conversion for channel 1 and analog output.
0: D/A conversion for channel 1 and analog output (DA1)
are disabled
1: D/A conversion for channel 1 and analog output (DA1)
are enabled
Controls D/A conversion for channel 0 and analog output.
0: D/A conversion for channel 0 and analog output (DA0)
are disabled
1: D/A conversion for channel 0 and analog output (DA0)
are enabled
Reserved
These bits are always read as 1. The write value should
always be 1. If 0 is written to these bits, correct operation
cannot be guaranteed.
Rev. 1.00 Oct. 01, 2007 Page 1676 of 1956
REJ09B0256-0100